Area Efficient Vedic Multiplier for Digital Signal Processing Applications

This paper proposes a method for area efficient fractional fixed point(Q-format) multiplier based on Urdhava Tiryakbhyam of vedic mathematics. Even though conventional or normal Urdhava multipliers carries high speed mathematical operations, they consume more chip area. Hence we proposed a pipelined multiplier architecture in this paper which consumes less chip area. The pipelined multiplier architecture consists of 3 stages. 1 stage consists of the n bit vedic multiplication unit. 2 stage consists of partial products and carry. 3 stage consists of adders and the result of the multiplication. This paper presents the efficiency interms of area for Urdhva Triyakbhyam Vedic methods of both conventional and proposed multipliers. The proposed algorithm is modeled using Verilog, a hardware description language. Implementation has been done for the Xilinx FPGA device, Spartan-3E. The results shows that multiplier implemented using pipelined Vedic multiplication is efficient in terms of area compared to its implementation using normal Urdhava multiplication method . KeywordsQ-format; fixed point arithmetic ;Vedic Mathematics; Urdhva Tiryakbhyam Sutra; Booth Multiplier; High Speed.